1. Field of the Invention
The embodiments of the invention generally relate to clock delay line sharing, and, more particularly, to delay locked loop clock recovery circuits.
2. Description of the Related Art
Binary weighted delay lines are commonly used in delay locked loop (DLL) clock recovery circuits. The DLL must add delay so that the output data is aligned to the external clock. The delay added is equal to the external clock cycle time, minus all fixed internal delays assumed in receiving, managing, distributing, and driving the clock through the OCD (Off Chip Driver). One of the difficulties in using a binary weighted DLL line is that one must find an appropriate time to update the control bits which control how much delay the line is to add to the clock path. The update must occur at a time that does not affect any current delay that is being managed by the DLL line. In practical situations, it is possible to have a continuously transitioning delay line, where there is no stable time to update the control bits. Any attempt to update the delay line while it is transitioning can result in spurious pulses being generated by transitional glitches.
One method used in the art to resolve the dilemma pose by delays through the circuit is to create a pulse whose duration is a fraction of the incoming clocks pulse to send through the delay line. Because of the reduced duty cycle, it is possible to create a period of time when the delay line is idle and can be updated. In this method the pulse must be carefully sized so that it remains valid for all process possibilities, and must be resized with each technology change and application to ensure functionality and avoid timing hazards. Thus, the update window is small and completely dependent upon the pulse width and internal clock path delays. In addition, longer cycle times require the pulse to travel the delay for a longer period of time, increasing risk due to pulse width modulation.
U.S. Pat. No. 7,061,287, herein incorporated by reference, is directed to a delay locked loop that is reset to the initial state when a frequency of the clock applied from an external chipset is varied.
U.S. Pat. No. 6,956,415, herein incorporated by reference, provides a modular DLL architecture capable of generating a plurality of multiple phase clock signals for synchronization of embedded DRAM systems with on chip timing.
U.S. Pat. No. 5,604,775, herein incorporated by reference, provides for a DLL clock circuit having multiple delay lines.
U.S. Pat. No. 5,604,775, herein incorporated by reference, teaches a delay-locked loop circuit including a variable delay circuit that outputs a delayed clock signal.